In my system I do not need deterministic latency offered by JESD204B subclass 1, so I want to operate in subclass 0 (so I do not need SYSREF signal). On the other hand, I want to install the ADC circuitry and FPGA in different locations connected together with QSFP cable. I see a potential problem with passing SYNCINB signal from FPGA back to AD9680 because a QSFP link is not DC-coupled (this is necessary for SYNCINB). In such a case: do I need to pass the SYNCINB signal from FPGA to AD9680?
if NO, how to configure AD9680 to work without SYNCINB signal?
If YES, do you see a solution to use links from QSFP cable? (I always can use another cable, but I would do this only if absolutely necessary)