I designed a board using Altera CycloneIV GX FPGA and AD7626. I followed CN0105. I maintained separate power planes, and also followed the recommendations for AGND/DGND. The ADC was working beautifully for sampling rates upto 1 MHz. But above this rate, I am observing horrible behavior. I have followed the timing requirements carefully. Unfortunately I don't have any signal integrity tool here. Nor do I have the ADC evaluation software or test-jig.
I feel that the problem lies in the sampling clock coming from the digital domain. The clock is driven by the FPGA. For 1 MSps rate, the sampling clock is 20 MHz. I feel that at this rate, analog domain is not getting polluted. But if I have to sample at 10 MSps, I need to drive the sampling clock at 200 MHz. I think this is creating havoc in the analog domain.
The main issue is that the ADC has serial output. So the converted data needs to be driven out at a high rate. Is it recommended that parallel output ADCs be used for higher sampling rates.
Any thoughts/feedbacks will be highly appreciated.