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AD9467 : Very High Dynamic Application, fs/2^17 Spurs

Question asked by Aot on Jul 2, 2015
Latest reply on Jul 27, 2015 by Aot



We use in our application an AD9467 ADC.

And use it with an FPGA connected to an CPU module.

In the FPGA we have several decimation, digital mixer and filter stages.

So we are able to aquire incredible low bandwidth signals with a superior SNR performance.


In values :

B = 20kHz

fbin ca. 0.1525Hz

N = 2097152 Samples (output, decimated, filtered)

Nadc = 1572864000 Samples (ADC input)

SNR > 155dBFS


With this we are able to see this: (FFT Spectrum, 5MHz offset, 20kHz, terminated ADC input)


We have a equally spaced spur rake with a distance 1.83105...kHz.

We found this spurs over the hole nyquist band. with nearly equal amplitude.

If we calculate the time domain value of this spur rake, we have a signale which has a glitch all 2^17 adc samples.

The glitch is time variant but highly synchronous with the 240MHz Sampling clock.

The glitch amplitude is around 4.6mVpp (this is around the 7/8'the adc Bit). But because of the ADC Noise you see this effect only if you have "big sample numbers".

This effect could come from our FPGA code, but we didn't found any evidence that the FPGA makes something wrong at the moment.

And we didn't found any evidence, that this effect is not generated by the ADC.

At the moment we are design a new FPGA bitstream so we can debug the raw ADC Data.

But now we are "blind" for what happens between the ADC and half of the FPGA code.


So in the meantime I would like to ask you :

Do you know that effect?

Is there any ADC internal which divides the clock with a 2^17 ratio?

Are you capable of measure this behavior with one of your development tools? (remember, you need around 240MSamplesx16Bit to see this phenomena! ==> 480MBytes of raw data)

Did you ever measure a sequence with such a high sampling time?

Are there any charge pumps active in the AD9467? Could they be a problem?

Are there possibilities to deactivate unneeded features? Like the PRN Generator (with p.Example undocumented registers?)

What actually happens, when I deactivate the Analog Input (SPI Reg 0x0F -> Analog Disconnect = 1).

What are the internal clock frequencies? (I mean internally on the die)


Thanks for your time


Alexander Ott