What is the reason for a 250MHz minimum frequency for SYSCLK on the 9912 DDS? I would like to run it at 100MHz or lower.
It seems peculiar that it would have a lower frequency limit. What sets the lower frequency limit? Thanks
The 250MHz spec is the minimum speed requirement for the dividers in the internal clock tree.
We are currently looking on this inquiry.
By the way, I suggest you also consider AD9910 which caters your input of 100MHz.
AD9910 can have clock input as low as 60MHz for disabled refclk multiplier.
The device should work running lower than 250 MHz System Clock. Part of the reason it is not specified below that frequency was to reduce the effort needed for evaluation; it was deemed likely that folks needing to run slower would look to some of the lower speed DDS devices available (e.g. AD9954)
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