Using DDS chipsset , Is it possible to extend DAC output width to 16Bits .
Sorry for my poor english
The DAC that our full-DDS portfolio uses only up to 14-bit resolution. However, if you do want to extend the DDS capability, I recommend to use a high speed 16 bit DAC such as AD9122, then create high speed DDS logic in an FPGA and use it in tandem with the DAC.
Using some logic coupled with 16 bit DAC was my first design choice , All driven by an AD5932.
Using lowpower DDS chips is an alternative very attractive....
I Thank you for your support.
I'd challenge whether you really need 16 bits. Consider a 16-bit DAC running at a 100 MHz full-scale sine wave, the DAC goes through one bit in 1 / (32768 * 2 * pi * 100M) = 48.6 femtoseconds. Your FPGA jitter is likely to be 1000 times this value.
I have a lot of faith in the designers at ADI, and I suspect the reason they didn't build a high-speed 16-bit version as you describe is because it doesn't make any sense to have that much precision in the DAC when the clock source can't match that level of precision.
I don't think the OP is attempting to generate a 100MHz sine wave at 16 bits.
There are other applications for DDS than RF.
Driving a piezo resonator for example might only need a 30kHz output but would benefit from very high frequency resolution due to the high Q of the actuator. This can be done with a relatively slow DAC with higher resolution and a shaping filter to remove spurs that can upset the resonance.
Also additional bits could be used to adjust gain without having to add an external multiplying DAC or analog gain adjustments.
Retrieving data ...