AnsweredAssumed Answered

AD9361 Setup timing violation

Question asked by MaxPayne on Jun 30, 2015
Latest reply on Sep 15, 2015 by larsc

Hello,

 

I am working on VC707 board with fmcomms2 HDL, 2015_R1.

 

When I make a very small modification, I receive timing problems at the end of the implementation phase. All of the violations come from "mmcm_clkout0" to "rx_clk", in the ad9361_dac_dma module.

 

How could I get rid of this problem?

 

Regards,

Max

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