I was trying the new HDL Reference Design hdl_2015_r1 with vivado 2014.4.1 to a zed board
I build all the necessary libraries and when I run the project by the system_project.tcl it seems to be work fine but if I reset the synthesis and the implementation and run it on the GUI show up the critical warnings:
[Route 35-39] The design did not meet timing requirements. Please run report_timing_summary for detailed reports.
[Timing 38-282] The design failed to meet the timing requirements. Please see the timing summary report for details on the timing violations.
Am I doing something wrong? I want to do some modifications on the project but without any change it is already giving an error.