I'M using the AD9910 to generate FMCW waveforms (e.g. 100 - 200MHz).
The big challenge is to set up a synchronisation environment that allows me to trigger the waveform with the lowest possible trigger jitter. Thereby I mean that that the time from trigger pulse (e.g. established by an I/O_Update) to the moment the waveform appears at the output should always be the same and vary by not more than 1 ps.
I understand that I need to synchronise the trigger pulse to the SYNC_CLK of the DDS to achieve this. I'm using 1GHz as the master clock, hence my SYNC_CLK has a frequency of 250MHz.
It's not that easy to establish a sync environment like that in the lab but in my final application I will use an FPGA for this task so this should be no problem.
Now comes the challenge:
I have another aux signal in my system that runs on a frequency of ~117.2 MHz. The FMCW waveform has to be coherent with this aux signal, too. That means, a rising edge of aux and the start of the fmcw waveform must always have the same delay. But a FMCW waveform start has to be synchronised to the internal 1GHz / 4 SYNC_CLK. To clarify that I attached a jpg file.
The problem is, that the aux rfequency of ~117.2MHz and the SYNC_CLK of 250MHz have nothing in common.
Sadly, I can't use another master clock than 1GHz (a master clock with a multiple of 117.2 would generate a SYNC_CLK frequency that is coherent to 117.2 MHz - but thats not possible in my system).
Do you have any suggestions? Is there a possibility to asynchronously trigger the DDS so that I don't have to wait for a rising edge of SYNC_CLK?
Any help or ideas are very much appreciated ... maybe anyone has a similar problem and found a solution to it