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AD9742 CLK+ input voltage

Question asked by MAPS346 on Jun 30, 2015
Latest reply on Jun 30, 2015 by MAPS346

Hello.

 

It is a question concerning data sheet page 14 CLK INPUT(LFCSP Package) of AD9742.

Single-ended clock input mode, CLK + input has been described as rail-to-rail.

 

How many input voltage is rail-to-rail?

(AVDD = 3.3 V, DVDD = 3.3 V, CLKVDD = 3.3 V)

CLK+: Min 0V, Max 3.3V?

 

 

Thank you!

 

Best regards.

MAPS346

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