accordingly to datasheet information the VDD must ramp up within 100us.
If this could not be met, is it possible to activate the RESET input until VDD is up and stable?
My colleague has responded and offered that the reset line was not operational during the "problem states" that poor power supplies would put the device into. At this point, awareness is probably enough but you might want to consider a mechanism for power cycle if a failed state is detected.
Thank you for posting this question. Based on my recollection, I believe that this will help with any sensitivity to the ramp rate, but it will not help if the supply has high source impedance. I will do some research on this to see if I can find out anything else on this matter and will post again if I find out anything else. Just FYI, we have seen sensitivity to ramp rate in less than 0.5% of our known applications but want to communicate observable sensitivities when even one customer brings them to our attention. I hope that helps.
BTW, you probably saw this, but just in case you are looking for a way to meet the 100us suggestion, this post might be helpful.
FAQ: ADIS1620x/21x/22x Power Regulator Suggestion
yes, I'm aware of the ADP1712, but I allready have a MAX8881 and a XC6221 3.3V regs.
In my prototypes I used MAX8881 with a risetime about 600us, and it worked well.
I am glad that is working well for you. This has been shared with a key colleague for review as well. He is pretty busy so this might take a couple of days to add any feedback he has.
thank you for info. Maybe you should put that in the 16209 datasheet.
My 16209 will have its own 3.3V regulator wich can be dis/en-abled.
Thank you for the feedback on this. I will give that some thought and look for ways to clarify this in future revisions of the datasheet.
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