I am trying to get the Zed Board with FMComms3 (AD9361) working in an bare metal OS configuration using the example code checked into the ad9361 git repository.
I have used existing FMComms2 pre-built HW platform output files and also re-built an FMComms2 HW hdl project and used those files for the HW Platform Specification in the Xilinx SDK.
I then created a BSP based off the HW platform and then compiled the AD9361 bare Non-OS code using the XILINX_PLATFORM compile time specification.
My project for the most part runs fine. The TX|RX LOs and remaining parameters seem to set up just fine.
I try to read the DMA register address (0x80000000) that should be linked to the AD9361 ADC and I get no change in output when monitoring the Memory location 0x80000000 (+ the size of my capture).
1) Should the DMA work correctly with the Non-OS code and FMComms2 hdl files?
2) If not, can you please LMK what the correct DMA configuration is for the example AD9361 Non-OS program is? Hopefully, I don't have to create a new HW platform...
3) If so, what is the best way to debug this issue?