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[ADV7390] SDA pin outputs high during power-up.

Question asked by Tamu on Jun 29, 2015
Latest reply on Jul 21, 2015 by Tamu

Hello,

I have questions about ADV7390.

 

My customer uses ADV7390 for their system.

There is a description about "Power Supply Sequencing" on the data sheet as follows:
  The ADV739x is robust to all power supply sequencing combinations.
  Any sequence can be used. However, all power supplies should settle to their nominal voltages within one second.

 

The power up sequence of his system is VDD_IO(3.3V) => VDD(1.8V).
The pull-up power for SDA pin is separated from VDD_IO supply.
He confirms SDA pin outputs high while VDD_IO(3.3V) is ON, VDD(1.8V) is OFF and other 3.3V supply for pull-up of SDA is OFF during power up.
SDA becomes low after VDD(1.8V) is supplied.
The reset pin is tied to GND with pull-down.

 

Questions:
  Why does SDA output high above the situation?
  Does power up sequence have to be VDD(1.8V) => VDD_IO(3.3V) or same timing so that SDA keeps low during power up?

 

The pull-up power for SDA pin is separated from VDD_IO supply.
It's not ON when SDA pin outputs high. So we don't think he sees the pull-up power 3.3V on SDA.

 

Thank you.
Best regards.

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