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AD9361 sampling frequency issue

Question asked by I-Feng on Jun 29, 2015
Latest reply on Jul 15, 2015 by mhennerich

I use AD9361 bare metal program and cloned from the ADI public git repositories with revision7b31ea970784307e7bb79647b8983769cbbf7946.


1. For Sampling frequency =56Mhz

If we based on ADI api, we will generate tx_path_rates (as Set1)

Set1= BBPLL:895999995 DAC:223999998 T2:111999999 T1:111999999 TF:111999999 TXSAMP:55999999


The Tx path could not transmit any signal.


If we modified API code

In ad9361_api.c

     phy->rate_governor=1(origianl) modified to phy->rate_governor=0  (This means highest OSR)


In ad9361.h

    #define MAX_ADC_CLK=640000000UL(origianl) modified to =680000000UL

we will get another  tx_path_rates (as Set2)

Set2=BBPLL:1344000004 DAC:336000001 T2:112000000 T1:112000000 TF:112000000 TXSAMP:56000000


Then TX path can generator normal signal.


My question is what is highest OSR? and why MAX_ADC_CLK=640000000UL?


2. For Sampling frequency =33.6Mhz

If we change the sampling frequency to 33.6Mhz, the Tx EVM and constellation are bad.

Could anyone help to check AD9361 register setting in attaching file?