On page 55 under Synchronization Timing, the spec reads:
“When more than one AD973x must be synchronized or when a constant group delay must be maintained, the internal controllers cannot be used.”
1.) From the above statement, I would assume both the LVDS and sync controllers should not be used. I can understand why the sync
controller shouldn’t be used because the FIFO possibly can add a random delay between two different DACs. What if the FIFOSTAT<2:0> value was the same for each DAC? Why shouldn’t the LVDS controller be used?
2.) This question may be rendered moot by the first, but I will ask anyways. Register 0x07 bit 3 specifies if the FIFOSTAT<3:0> is valid. Even after resetting the DAC, register 0x07 bit 3 never goes high. I reset the DAC by writing to register 0 bit 5. I set bit 5 high and then clear it. I have verified that the reset successfully clears register 5. Why isn’t the valid signal going high?
3.) Can I use the BIST feature as a way to verify the data and the clock going into the DAC are producing a good clean output waveform?