Do any of the ADC interfaces in any of the reference designs use the default DDR two lane configuration to output data? Or any of the two lane options? I am looking for an HDL reference. Thanks.
You have already found the only design (AD9279) that is close to this. If you are having trouble -- post the code and/or plots here-- we will try to help.
You may want to rephrase your question --
All our interface uses 'default' configuration (DDR or otherwise)-- & there are no 'default DDR two lane configuration to output data'.
You are right, allow me to rephrase.
I am using AD9633 in serial data mode 0x42 (DDR one-lane). I had modified the reference design for AD9279 to read data from the 9633 in this format, which was very useful to me. However, the AD9633 has a default configuration that outputs data in a serial data mode of DDR two-lane bytewise. In the 12-bit version, this means the bit clock would be 3 times the sampling clock, instead of 6 times the frame clock as in the single lane configuration. I am inquiring whether any of the AD FPGA reference designs for ADC interfaces are designed to capture data in the DDR two-lane format, so I can possibly use it as a learning tool to modify my design and use all 8 lanes to output the data of the 4 channel ADC. Can you point me at any such reference design?
Retrieving data ...