Reference clock level of HMC6000LP711E

Discussion created by lingyun on Jun 24, 2015



I am confused about the reference clock level used for HMC6000LP711E.

In the Table 3 of datasheet, the recommended reference clock is 3.3 or 2.5 V LVPECL/LVDS 1.2V CMOS, but in Table 5, the absolute maximum rating for each reference clock input is 0.75 Vpp (AC coupled). Are these two contradictory?

Now I am using a sinusoidal signal with 1.2 Vpp and 0 V common mode to feed a balun, whose differential outputs are connected to REFCLKP and REFCLKM. Is this the right way to feed these two pins?


Thank you,