The ROW15<7> and ROW15<6> are 00 now, which indicates the VCO control voltage below lock window.
How can I make the VCO control voltage within the lock window and have synthesizer locked?
The reference clock 308.5714 MHz is used and chip is setup to work at 60.48 GHz (IEEE CH2). The divider setting 11111 and typical band setting 100 have been successfully written to registers.
The reading of ROW10 is shown below, which is 10001111. The green line indicates the Enable signal and yellow line indicates the Scanout signal.
The reading of ROW11 is shown below, which is 10011111.
The reading of ROW15 is shown below, which is 11100100.