I am using the ADF4351 PLL with the following setup
- Reference frequency = 26 MHz
- Integer-N PLL
- Output frequency = 2470MHz
- Disable doubler
- disable divide by 2
- R = 1
- 25kHz loop filter for CP = 2.5mA
CP is set to 0 => reference spurs at +/-26MHz < 87.5dBc
CP is set to 15 => reference spurs at +/-26MHz < 81.3dBc
In Table 1, spurious signals due to PFD frequency is specified at -80 dBc.
Does it mean that the reference spurs is at -80dBc? Does it take into account possible feedthrough?