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SSM2604 MCLK Clarification

Question asked by samsonian on Jun 23, 2015
Latest reply on Dec 10, 2015 by DaveThib



I have a customer using the SSM2604 and they would like some clarification on MCLK. If they go beyond the specified MAX Tolerance of 13.8 MHz then they will essentially need to set CLKDIV2 = 1 therefore, effectively forcing them to use an MCLK frequency >= 16 MHz since core clock min tolerance is 8MHz correct? Also, I noticed that Table 26 on page 23 of the SSM2604 Datasheet is somewhat incorrect since there are MCLK/2 values greater than the max tolerance of 13.8MHz. In further investigating, it seems that Table 26 is essentially a copy and paste from the SSM2603 datasheet...the 2603 has a wider core clock tolerance of 8MHz to 18.5MHz which would explain the larger values in the table. Thank you for your help