With the introduction of the ADF4158 & ADF4159 data sheets, I simulate the PLL frequency domain and time domain response with ADIsimPLL software. However, the ADF4158 output on my test board is quite different from the software simulation result . There are 2 continuous sawtooth with FSK ramp enabled waveforms I try to test on the board, one waveform with FSK DEV -120kHz, and another one is 120kHz. From the ADIsimPLL simulation result, the time domain of the 2 is obvious different when loop filter bandwidth set to 800kHz, but I have a conclusion that the 2 waveforms output from ADF4158 on the test board are almost the same in fact after analyzing the data and algorithm in my radar system. I doubt that the loop filter design is not proper for the system, but I don't know how to design an ideal loop filter matching to the system. Can you tell me how many factors should be considered when designing a loop filter and how to determine the correspoding parameters? The ADIsimPLL .pll simulation files are attached and PFD is 10MHz, each step in the ramp lasts 6.4us.
The attached .pll files are generated with ADIsimPLL 3.60.10.