Hi Everyone,

I'm trying to measure a complex impedance from a frequency range of 10Hz up to 1KHz with 1Hz resolution. I've a programmable MCLK source. I have the following issues:

1. How could I correctly measure impedance at a single frequency? Currently I'm measuring with a desired Start frequency and using frequency_increment = 0, and number_of_increments = 0. Is this correct?

2. For the desired frequency output, I'm calculating MCLK by using the formula:

**MCLK = Output_freq * 16 * 1024 / Number_of_settling_time_cycles**

Is this formula correct? (I have found it out here: https://ez.analog.com/message/204632#204632)

3. While observing the excitation output, I observe spikes at each frequency sweep time instant. i.e. whenever a frequency sweep is initiated by the command, a spike is observed in the output which is causing erroneous impedance results.

4. Is there any optimum criteria for determining the number of settling time cycles?

Please help!

Thanks and regards,

Shehzad

Hi Shehzad,

As a response to your issues:

1. You can set the number_of_increments to at least 1 and the frequency_increment to 0.001Hz. Starting from 10Hz, you can do a sweep that would be from 10Hz to 10.001Hz then change your start frequency to 11Hz and do a sweep again. With this setting you can do single frequency impedance measurement without changing your MCLK. If the 0.001Hz sweep for each start frequency would not be an issue for you.

2. Yes, you can use that formula to calculate for your MCLK. You can also use this for single frequency impedance measurement but I do not know what would be the setting for the number_of_increments and frequency_increment for this method.

3. Can you try to observe your excitation output using the new settings for your number_of_increments and frequency_increment?

4. The settling time cycles determines the number of output excitation cycles that are allowed to pass through the unknown impedance before the ADC is triggered to perform a conversion of the response signal. Thus, it determines the delay between the start of the frequency sweep and the time the ADC conversion commences.

Best regards,

Mark