We are using table 113 settings and 27MHz is the clock.
I want to know in 864 pixel points from which clock count the line should start and which will be first active line expected by ADV7391.
Also please clarify if Table 113 is used and the sync signals(HSYNC and VSYNC) aregenerated by me from FPGA for giving to VGA connector. How the synchronization of pixel start in each line and pixel start expected by the IC happens?
I am giving EAV and SAV codes also during start of line and end of line, with F V H values as below.
F= 0 always as progressive video
V=1 during blank lines else 0
H =1 during blank lines and EAV and 0 during SAV
We are having one layer of patterns going above video and a black horizontal
bar which scrolls up is coming?
Doubt is if EAV SAV synchronization is used how HSYNC and VSYNC are matched to it.