I am working with IC AD7747 to measure the capacitance in pf range. How does this work especially 24 bit sigms delta generator and CAPDAC part ?
What is the internal circuit diagram of this IC?
It is a charge balancing circuit with a sigma delta ADC. See the attached document for some more details.
Thank you for your help.
I tried to understand the working by reading the pdf you attached but I am new to this field so it is becoming difficult to understand. Like how the comparator in giving the digital output, what is it actually representing and how it is changing f1 and f2, Is it like capaciors are switched during each ph1 and ph2 like once the charge of cref and then cin is transferred ?
Can you please give some more detailed explaination on this.
I have one more doubt. I am trying to measure capacitance between the range of 0 to 8 pf using AD7747. When I am measuring a capacitance Cin is fixed then how will the charge balancing technique will work as the excitation voltage is also fixed when we program the IC. I took the reference of page 4 in the pdf you attached.
I have attached a Webinar on these parts that should help with your understanding. We normally don't go into architecture discussions on circuit designs on this forum. In summary this part is essentially an ADC that works using a charge balancing approach, there is an known internal fixed capacitor that is compared to the external capacitance and the value of which can be determined.
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