I’m interested in building a high speed high precision digital control loop design with the AD7760. In my project I use the evaluation kit EVAL-7760 and an additional FPGA to configure the ADC. For a proper behavior of the loop it is recommended that the delay time in the loop is as short as possible. That’s why I have to use the “modulator output mode” option of the AD7760. To achieve this mode I write a zero in register address 0x0001 to the bypass filter bits D4 and D3 and in the decimation bits D2 to D0. The clock divider bit in register 0x0002 is zero or one in dependency of the oscillator I use (20MHz or 40MHz).
After that I compute the delay from the ADC from analog input to digital output. Therefor I feed the AD7760 with a symmetrical 2Vpp rectangle signal and compare this with the upper bits of the digital output (the output is represented in a two’s complement). In my setup I found out, that the AD7760 has a propagation delay of approximately 350ns (see attached image below). For my control loop design this value is very bad. Also I think I do something wrong by setting up the register of the device, because the datasheet denoted a delay of 0 for an unfiltered use of the AD7760 (Table 6 on Page 18).
Can anyone give me an advice what I’m doing wrong or how I can achieve a shorter computation delay of the device?
yellow: analog input signal (rectangle)
green: data ready signal
blue/green/purple: digital output D15 to D0