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Interrupt Handling and DMA

Question asked by Shafi on Apr 5, 2011
Latest reply on Apr 7, 2011 by Prashant

Hi ,


    I am using SPORT0 in my application for interfacing to an ADC. I have used the default DMA functionality of the SPORT0_TX(DMA4) and SPORT0_RX(DMA3). Also I have used Interrupts for both the DMA's. I am using PPI(DMA0) for another purpose but i haven't enabled the interrupt for DMA0. DMA3 and DMA4 are working in Autobuffer mode and the issue that i am facing here is with Interrupt handlers.



This is how i have assigned the Interrupts




#define SPORT0_RX_IVG(x)              (P16_IVG(x))
#define SPORT0_RX_IVG_MASK      (~SPORT0_RX_IVG(0xF+7))
#define SPORT0_TX_IVG(x)              (P17_IVG(x))
#define SPORT0_TX_IVG_MASK       (~SPORT0_TX_IVG(0xF+7))


void InitInterrupts()

*pSIC_IAR2  &= SPORT0_TX_IVG_MASK; // prepare a spot for this mapping
*pSIC_IAR2  |= SPORT0_TX_IVG(8);  // map Sport0 Tx (DMA4) to IVG8
    *pSIC_IMASK0 |= IRQ_DMA4;          // enable the interrupt

*pSIC_IAR2  &= SPORT0_RX_IVG_MASK; // prepare a spot for this mapping
*pSIC_IAR2  |= SPORT0_RX_IVG(9);  // map Sport0 Rx (DMA3) to IVG9
    *pSIC_IMASK0 |= IRQ_DMA3;          // enable the interrupt




But the problem is , once i start running the application, and once the SPORT's have been enabled , it doesnt ever get  into the TX Interrupt Handler. I tried by putting breakpoints in both the interrupt handlers. The observation was that it first goes to the TX_interrupt handler breakpoint as expected and then doesn't come out of that. If I enable breakpoint in the RX_interrupt handler it just enters the Tx_interrupt handler only once although my DMA4 is working in Autobuffer mode,it then keeps on hitting the breakpoint in the RX_interrupt handler, but doesnt go to the breakpoint in the TX_interrupt handler. Is the Autobuffer mode creating problems here? I need TX_interrupt handler because i need to do some timing manipulations with that.



I have attached a screenshot of the Register contents of DMA3,DMA4 and DMA0 and SPORT0_STAT.