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RAM_SWP_OVR Timing Mismatch AD9910

Question asked by dabenPB on Jun 21, 2015
Latest reply on Jun 25, 2015 by Kevin.G

I am evaluating the AD9910 EVAL, and have a question about timing of the RAM.  Specifically, I have loaded a single set of FTW in RAM profile 0 from address [0,82].  RAM data type is frequency.  The FTW span [0,10:50,0] MHz where each word from 10:50 increments by 0.5 MHz.  When I  monitor the RAM_SWP_OVR pin and compare to the actual sweep, the RAM_SWP_OVR ends BEFORE the actual sweep (see attached).  I would have expected these to be coincident.  The sweep also starts late by the same amount.  My Address Step Rate is 0.008us and the System Clock is 1000 MHz.  It looks like this lag is about 62ns.  Can someone explain this lag since Figure 43 in the AD9910 document seems to indicate that they should be coincident.

 

Also, I have added the DC on both sides of the FTW words to "shut off" the generator.  Is there a better way to disable output than this (I know Clear Phase Accumulator does this but it takes an IO_UPDATE)?

 

 

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