Right now I am interfacing Pmod AD5 (which has a AD7193 chip) with a FPGA board. I am new to this and don't really know much about it.
I am writting a verilog code. I have read the datasheet of AD7193 as well as of Pmod AD5. I have gone through the other discussions on this forum and they have really helped me a lot. So coming to my question.
I am writting code using finite state machine.
I first set the sclk frequency as 100Hz(using simple clock divider circuit). I reset the ad7193 by sending 40 1's(MOSI=1) and then wait for one clock cycle(for 0.1s >> 0.5ms) and then tried to write and read back from the mode and configuration register. I was able to do this.
Now I set the sclk frequency to 2500Hz. Reset the ad7193. And I want to add delay state of 1ms (1/2500=0.4ms).
As I need sclk to idle high (MOSI is still high), during this delay, when no read or write operation is carried out. I tried but I am not able to do this.
This seems very easy though.
Can I get any code of how to make sclk idle high when needed and it operates at its desired frequency during any read or write operation?
It would be really very helpful.