I cannot find the relationship between RESET and SCLK for serial operation. Should RESET be synchronous with SCLK or does it not matter?
In all modes, the parts should receive a RESET pulse after power-up. The reset high pulse should be typically 100 ns wide. Just note that after the RESET pulse, the AD7656 needs to see a valid CONVST pulse to initiate a conversion; this should consist of a high-to-low CONVST edge followed by a low-to-high CONVST edge. The CONVST signal should be high during the RESET pulse.
Hope this helps.
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