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BF54x DDR interface, DQM, DQS signals

Question asked by RichardJ on Apr 4, 2011
Latest reply on Apr 6, 2011 by WassimB

I need a bit more info regarding the connection o DDR SDRAMs to a BF54x. I'm putting together a new design using the BF547, with its DDR SDRAM memory space fully populated, i.e. eight 512Mbit devices, each having a x4-bit bus. I've not been able to track down the how DQS[1:0] and DQM[1:0} correspond to the DDR data bus bits, any clues? If I were to guess then I'd go for DQS0 and DQM0 go with D[8:0], but that's not something I've been able to confirm yet.


With reference to BF547 hardware ref manual 0.5

page 5.37 briefly mentions the masks apply to writes only, but not their byte mapping.


Page 5-39 states all but DQM[1:0] are common to all SDRAM chips, these two must match the data bits with which they are associated, but doesn't give the association. This also seems in error, what about DQS[1:0]?


Page 5-40 has a block diagram that's missing quite a bit of important annotation: The 16-bit bus splits, but how. Likewise DQS[1:0] and DQM[1:0]. This diagram is very similar to one in the BF533 manual, this time giving the split, are they the same? I'm reluctant to take the plunge on an educated guess.