I'm designing a product which uses the AD7689 near full speed (210 kSps), scanning each channel successively . All of the inputs are nominally at the same midscale value. If one channel deviates from the others even by 50mV, an FPGA will attempt to bring it under control.
If the channel-to-channel differences are small, is it OK to use 1/4 bandwidth? If I understand the architecture correctly, the SHA is not zeroed out between conversions. Thanks!