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Extra Bits in ADC Data on AD-FMCJESDADC1-EZB Reference Design

Question asked by e.r.i.c on Jun 18, 2015
Latest reply on Jun 18, 2015 by rejeesh

In the ad-fmcjesdadc1-ebz reference design, when I look at the output of the ADCs in Vivado's Hardware Manager each of the ADC outputs is 32 bits wide. However the ADC is only 14 bits wide. I understand that the ADC actually outputs 16 bits per channel, and the 2 LSBs are not part of the data. What I don't understand is where the other 16 bits are coming from. I have looked through the reference design, but I am still not understanding it.

I can also see that the DMAC module receives 64 bits. The lower 16 bits from both channels make up the lower 32 bits that the DMAC receives, and the upper 16 bits from both channels make up the upper 32 bits of that the DMAC receives (assuming both ADC channels are enabled). However, in the bare-metal software, I run the adc_capture function, then read 32 bits from memory. This 32 bits contains the output of both channels of the ADC that I am targeting (16 bits each).

In short, I have a 2 channel 14-bit ADC as an input, and I am reading 16 bits of data per channel from memory. This makes sense to me. What I do not understand is why each individual channel has 32 bits in the hardware. Could someone please explain to me where the extra bits come from, and where they go after the DMAC module?