With the ADAU1701, I would like to create a single channel VOLTAGE CONTROLLED DELAY by the AUX ADC.
If I use the following set :
Does that mean that the delay is controlled by the aux ADC from 0 to 1.3ms, in 256 steps ?
In addition to the wiki, studying the -1701 and SRC data sheets will help you set up your chips properly. Searching EZ may also help, since this need has come up before. One post that appears relevant is:
https://ez.analog.com/message/179508#179508. I'm not particularly good with I2S, but there's others here that could assist you with any questions you encounter as you plan your design.
Most of us originally came to EZ looking for help, then once finding our own sea legs, we discovered the joy of helping others learn the ropes. Your chance may come sooner than you realize, when you observe someone struggling with some issue which you have already figured out.
It should work according to the documentation (in the built-in help, I didn't check the wiki), but it doesn't. A quick test reveals that the Voltage-Controlled Delay works with 0 to 1.0 analog (5.23 format) input, not 0 to (# of samples) integer. You can simply get rid of the multiplier and tie the Aux ADC directly, then you'll get a variable delay.
Also since you're running at 192K, be sure to set the Core Register in the HW Config to 4x (256 instructions).
Thank you again for your great help, but it does not work when I use only AUX _ADC input to control the delay.
My solution seems (seems...) working with a DC input (28.0 format) and a multiplier, I can hear the difference I need, but I don't know if it is the exact delay value.
I will connect the ADAU1701MINIZ EVB to an oscilloscope to test and to verify.
When I turn counterclockwise the potentiometer wired on the ADAU1701MINIZ EVB the delay increase continuously.
As it turns out, there's two kinds of voltage-variable delay -- the Fractional (interpolated) variety as well as non-fractional one. Once in a schematic, both delays appear the same. My comments above refer to the Fractional voltage-controlled delay. The non-fractional one uses the input that both you and the docs describe -- it accepts a 0-255 integer input to provide a 0-255 sample delay. I have both flavors of delay in the circuit below, and both work as expected with their respective inputs.
I attached the project file which runs on the ADAU1701MINIZ board. You'll hear the 769 Hz tone output with the pot at either end of its rotation (no delay, or a full cycle delay) -- and a minimum at the halfway point (180 degrees phase shift from 0.65 mS delay).
You are right I used the VC (not fractional) delay.
I tested your and my solution this morning and they work exactly as I expected.
Now the last problem I have to solve is the input select between the ADC audio input and the I2S input with an aux ADC. the I2S input is wired to an ASRC which convert the SPDIF input to 192kHz SRC.
I am a beginner and english is not my native langage, so It needs time to understand all parameters with internet wiki only. The engineer zone is a great help and I hope to help someone later.
Your solution will be tested next week.
Anyway thank you very much for your very useful help and I save a lot of time.
I hope to return a favor one day why not.
Have a nice sunday.
I just discovered I had to do a -1 to +1 input range to get the full range of delay: Testing with a sine wave oscillator is an easy method of checking the delay by phase cancellation:
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