I'm not able to understand the data flow between the ps7, vdma and DAC from the block diagram in the reference design hdl (AD-FMCOMMS2). Can you please elaborate the data flow from the ddr memory to DAC?
I've branched this into a new discussion as the other one was already more than two years old.
The current design no longer uses the VDMA but the AXI-DMAC for the DAC DMA, but that is just an implementation detail. The data flow is very similar in both cases.
On one side the DMA controller is connected via a AXI3 bus to the HP interconnect of the PS7 system, this gives it access to the main DDR memory. When instructed to do so the DMA controller will read data from the main memory via this port. On the other side the DMA controller is connected via a FIFO-interface to the AD9361 interface logic core (the AXI_AD9361). Once the DMA core has received data from the main memory it will send it out onto the other side to the AXI_AD9361 core via the FIFO interface. The AXI_AD9361 will take the data and convert it into the low-level LVDS signals that the AD9361 itself is capable of understanding. It will add framing and output the data onto the bus with respect to the interface clock. The AD9361 will receive the data and then eventually transmit it on the RF interface.
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