The pin assignment seems correct to me.
Note that the BF548 EZ-Kit also uses a 32M x16 DDR device. So you might want to check those schematics.
Thank you for your advice.
Hi, I would like to know whether I can open DCLK2/DCLK2~ and drive two DDR1s memory by DCLK1/DCLK1~ or not.
I think if my configuration is correct then I have to make a termination of DCLK2/DCLK2~. Can I open DCLK2/DCLK2~?
Or I should pull down weak for DCLK pins which is unused. I get good EMI performance with pull-down.
By the way, is DCLK1/DCLK1~ or DCLK2/DCLK2~ automatically disabled if I do not use it?
I do not see a description on Hardware reference manual of BF54x for a control method of DCLK pins.
I believe this query is already handled through private support channel (SR:1131355).
If you are not using DCLK2-DCLK2# clock pair, you can left those processor pins floating. This can be OK in terms of EMI. You can refer BF548 EZ-KIT schematic.
There is no register setting available to disable the unused clock pair.
BTW, as per inputs from one of my colleague:
When using multiple receivers off of one differential clock that this end up increasing the load capacitance of the clock.
A good point of contact is the following Micron EE-note: http://www.micron.com/get-document/?documentId=4922
Also if the customer is using multiple memory devices that they would need to length matched and routed in signal groups. Also any trace above 2” would need parallel termination in addition to series termination and possibly even a VTT tracking circuit etc. The Micron document mentioned above can be used for reference here.
Thank you for your reply.
I understand it.
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