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Configuration of ADV7604 for PAL input

Question asked by ces.gz on Mar 31, 2011
Latest reply on Apr 5, 2011 by DaveD

Hello,

 

I'm new with the configuration of the ADV7604 for analog and need some help to configure an analog-to-digital conversion.
I am trying to configure the chip to have correct analog to digital conversion of PAL video 576i to digital 4:2:2 at 27 MHz frequency, with chroma/luma interlaced on the same 8-bit bus.
Currently I have applied the configurations below through MicroBlaze and at the output I can only see rather constant very small values, after the usual FF 00 00 etc. The input is the standard "city" video, signal seems to be ok at the input pins. Also attached one file with the readbacks of the registers. Could someone kindly help with what may be missing/wrong or also would it be possible to post some examples ?

 

Thank you in advance,
Regards

 

Giorgio

 

//I/O MAP 

 

0x40 0x0c 0x40  // Power up CP core  //sync channel 1 only,power down disabled, operational chip    
0x40 0x00 0x03
0x40 0x01 0x11  //  SD 2x1 625i 720x576[5:0 @ 000011 ]
0x40 0x02 0xF4  // Forces YCrCb input (601 color space) (range 16 to 235)
                // default 8bit ITU SDR 656 mode ,default SDR 4:2:2[7:5 @ 000],[4:2 @000] mode 0 12 bit compatible output mode
0x40 0x03 0x00   
0x40 0x33 0x40  //LLC DLL enable
0x40 0x15 0x90  //Disable Tristate of Pins except for audio pins
0x40 0xe0 0x80  // downsamples and no filtering

 

//CP MAP 

0x44 0x85 0x1B               //Disable Autodetectmode for Sync_Source for CH1. Force CH1 to use Embedded Sync.   
0x44 0x3E 0x04               //adi
0x44 0x40 0xF3               //ADI for ESDP
0x44 0xc3 0x31              //adi
                
//AFE MAP 
   
//0x4C 0x02 0x80               //  [2:0 @000]Embedded Synch1,manual muxing etc.. 
//0x4c 0x03 0x12               // connections !IN to ADCs
//0x4C 0x04 0x30               //
0x4C 0xC6 0x5F               // disable audio core
0x4C 0x12 0x7B               //adi recommendations
0x4C 0x0C 0x1F
0x4C 0x05 0x07               // enable aa filters
0x4C 0x15 0x0F               //Adjusting clamp filter on Sync Channels for Sync > 2.5uS
  
// ESDP mode enable
0x40 0x0F 0x9E
0x70 0x00 0x05               //enable 576i to be detected
0x70 0x67 0x99               //set medium PLL
0x70 0x79 0xF1   
0x40 0x30 0x08
0x44 0x6C 0x00
0x44 0x73, 0xF2
0x44 0x74, 0x08
0x44 0x75, 0x82
0x44 0x76, 0x20
       
// ADC Input Range Control

 

0x4C 0x0F (data or 0x80)
0x4C 0x0C 0x1F
0x44 0x3E (data or 0x84)
0x44 0x40 0X60
     

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