I am using a Xilinx V6 FPGA to interface to an AD9129. The sample clock is 2.4 GHz, which puts the DCO at 600 MHz.
I use a MMCM_ADV to generate internal clocks - and implement the physical interface as described in Xilinx document XAPP1071. I have IODELAY cells in place to allow changing the delays.
Before and after running SED, I check the status of the DLL by reading register 0x0E, and it always reads 0x85.
The SED test only reports failures on the F0L, F0H, F1L, and F1H patterns - all the falling edge data.
Looking for any insights on how to proceed.