Hi every body,
I'm using a stratix 3 fpga to control DDS ad9914. I use the parallel mode to configure the register CFR and the direct mode to write amplitude,frequency and phase for modulation.
I have 2 problem:
the first problem is that i cannot visualise the amplitude modulation when i change the amplitude values in the register, although i have set OSK to enable and external OSK enable(bit 8,9 of CFR1). There is no change when i write or not write inside.
the second problem that i have is that i cannot visualise at the same time the DAC output and the synclk. when i activate the synclk bit (bit 8 of CFR2) the DAC output does not come, but when i disable the synclk bit the output come and the synclk amplitude come to 0 and the frequency is the right one.
i attach my C code so you would look if there is something wrong.