AnsweredAssumed Answered

DAG Register transfer restrictions

Question asked by IgnacioAOCS on Mar 29, 2011
Latest reply on Apr 6, 2011 by jeyanthi.jegadeesan

I'm working with a 21k processor. Picture the following very simple code:

 

m3=0x30;

r8=dm(m3,i3);

 

As the manual explains, the processor inserts a NOP between these two instructions, given that both involves the same DAG. When I hook with the scope, I see that the processor first asserts chip select, then waits a cycle (NOP) and finally changes the address in the DMA bus. This sequence is giving me much trouble, and the manual does not mention any such delay. If, instead, I insert an explicit NOP between them:

 

m3=0x30;

NOP;

r8=dm(m3,i3);

 

The chip select assertion and the change of the address in DMA bus occurs almost in the same time (this sequence gives me no trouble).

 

My question is, why the explicit NOP performs different that "implicit" NOP?

 

Thanks in advance.

 

Ignacio

Outcomes