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AD9361 LVDS timing

Question asked by cy92612 on Jun 13, 2015

I'm using the AD9361 in LVDS mode.  DATA_CLK = 61.44 MHz. 1R1T mode.

 

According to UG-570 page 110, the I samples are clocked out of the AD9361 on the rising edge of DATA_CLK.  They are to be clocked in the FPGA on the falling edge of the clock.  And, vice versa for the Q samples.  RX_FRAME changes on the rising edge of DATA_CLK.  Right?

 

However, I'm seeing that the I samples are clocked out of the AD9361 on the falling edge, and the Q samples on the rising edge.  RX_FRAME is clocked out on the rising edge, as expected.

 

I used the mask bits in register 0x3f6 to look at only I or Q samples.  I got to this point after finding that my I and Q samples were getting swapped.  Can someone explain this?  Is the datasheet wrong, or is there something I'm doing wrong?

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