Could someone clarify when active bits in IRQSTA will be cleared on the ADuC7024, and whether the clearing behaviour is applicable to all bits?
In another discussion it has been said "it is latched into IRQSTA and the relevant bit in IRQSTA will not get cleared until the interrupt is fully serviced" and also "the same bit in IRQSTA will stay set until the IRQSTA register is read". These seem like different behaviour.
I see that the interrupt system for the ADuC7023 and ADuC7034 must be different from the ADuC7024 as for these parts it says:
"IRQSTA/FIQSTA should be saved immediately upon entering the interrupt service routine (ISR) to ensure that all valid interrupt sources are serviced."
The ADuC7023 also says "FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits)", while the ADuC7034 says "IRQSTA provides the status of the IRQ source that is currently enabled (that is, a logic AND of the IRQSIG and IRQEN bits)".