Page 19 of ADV7511_Hardware_Users_Guide.pdf:
Various IOs say:
Supports typical CMOS logic levels from1.8V up to 3.3V
I don't see a pin that sets the IO voltage, is this correct?
Am I right to assume the high voltage threshold is just below 1V8 for both 1V8 and 3V3?
If this is correct I could mix IO voltages.
I have a 3V3 and a 1V8 bank on my FPGA, I would like to use 1V8 for the data and 3V3 for I2C. Can you confirm that this is ok?