We have designed a circuit board with the AD9361 and see some unexpected noise floor shapes when receiving 54 MHz of bandwidth through the chip. All of the bandwidths were created using the Matlab AD9361 plug-in. Attached are two spectral views. The first uses a 40 MHz bandwidth and shows a reasonably flat noise floor. The second view uses the 54 MHz filter but the noise floor at each end rises up about 10 dB then starts to tail off. The noise floor on the transmit output for both the 40 MHz and 54 MHz bandwidth are flat.
Are these noise floor lobes due to the sigma-delta ADC? Is there some way to get rid of or reduce them? The 54 MHz bandwidth uses an ADC rate of 480 MHz and a final sample rate of 60 MHz (decimate by 8). We can't run the ADC at a higher rate without violating the max transfer rate between the AD9361 and our FPGA since we use FDD mode and all channels (RX1, RX2, TX1 and TX2).