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ADV7181c

Question asked by Debs on Mar 28, 2011

Hi all,

 

         I am new to the Engineer Zone.

 

         I am currently working on a system which takes in CVBS(preferred) or VGA(less preferred) video input and converts it to 12-bit DDR 4:4:4 RGB output. I am using ADV7181c for this purpose. I hope that this chip is capable of doing that.

 

        The control to the chip is through Xilinx FPGA XC3S500E mounted on Digilent Nexys 2 board. I want to know what exactly are the registers in the chip that are to be configured/programmed to get this operation going?

 

        Also any ideas on how to actually create an I2C controller in FPGA which will configure the chip in the bginning of its operation? Means FPGA is the master here, and ADV7181c is the slave. The SCL clock will be generated by FPGA at 400 KHZ. On the SDA line, after the Start bit, one by one the (starting from MSB) the slave address, followed by acknowledge from slave, followed by register sub address, followed by ack from slave and finally data to be written will be sent, followed by ack form slave - am I right about the sequence?

 

       Please reply quickly to this post. Help is urgently required.

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