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An issue about AD9956

Question asked by hpkamen on Jun 11, 2015
Latest reply on Jun 14, 2015 by LouijieC

According to the datasheet, when the clk is setting at 400Mhz, the SYnc_clk should be  100Mhz. I set the register FSRR, RSRR as 0x01, so the time step Setting should be 10nS,  is that right?

if i am right, the step frequency should be  400MHz/2^24=23.84Hz, however, according the actual testing results, using setting FSRR, RSRR as 0x01,  it takes about 40uS to rise the frequency from 10Mhz to 35Mhz. And thus if the time step setting is 10nS, the step frequency should be 6Khz. So it seems contradicting with datasheet's description.

Please help me clarify it.

thanks.

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