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ADAV803 SRC clock question

Question asked by rmauro on Jun 11, 2015
Latest reply on Jun 11, 2015 by DaveThib

Table 2 on page 4 of the ADAV803 datasheet lists SRS MCLK Min = 138 x Fsmax but the text on page 21 states "The SRC master clock is expected to be equal to 256 times the output sample rate."   These appear to be conflicting statements..  Please help me understand.