There are some directions in ADSP-BF537 Blackfin Processor Hardware Reference about SPI SCK and \SS signals:
"The enable lead time (T1), the enable lag time (T2), and the sequential
transfer delay time (T3) each must always be greater than or equal to
one-half the SCK period."
On the figure it is shown that T1 is a time between sampling edge on SCK and \SS going to inactive, T2 - between \SS going to active and driving edge of SCK.
I experimented with transferring data from SPORT to SPI. SPI SCK was driven from SPORT TSCLK and SPI \SS was driven from SPORT TFS. SPORT drive its TSCLK and TFS simultaneously. Accordingly to Hardware Reference there must be a lag time between \SS and SCK, but data were received correctly.
Must ideed there be the lag time?
Is there any latent probability of faults when \SS and SCK are switching simultaneously?