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AD9956 Fractional Divider Loop

Question asked by JUST_ANOTHER_RF_GUY on Jun 10, 2015
Latest reply on Jun 11, 2015 by KennyG

Hello all,

 

  I am having a bit of trouble getting my head around the operation of the AD9956 when in the fractional-divider loop configuration shown in figure 23 of the datasheet.

fig23.png

 

 

My biggest stumbling block right now is how does one model or predict the response to the changing system clock?  If the system clock were from a stable (non-swept) source then I could see where the sweep of the PLLOSC frequency from the DDS output would cause the phase frequency detector to adjust the charge pump resulting in a sweep of the external VCO.  If I use the feedback of the VCO to generate the system clock as shown above, then my DDS is tuning the FTW at the same time that the phase frequency detector is changing the charge pump which in turn changes the system clock driving the DDS.  Given that the rate of the sweep is specified by a certain number of sync clock cycles (which is just the the system clock divided by 4) it seems to me that the linear sweep is no longer linear.  It is very possible that I am missing something basic, so any insight you care to offer is appreciated.

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