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Question asked by guorock Employee on Mar 24, 2011
Latest reply on Mar 25, 2011 by DSB

For AD9910, below is the requirement to REFCLK. When we apply single-ended input mode, the maximum amplitude of REFCLK is 1000mVpp.

Also in some other DDS Parts, for example, AD9956/8/9, we can find the similar requirement to REFCLK.

But many customer want to use external oscillator to supply REFCLK, but normally the oscillator is powered by 3.3V, so the oscillator's output will be 3.3Vpp, the amplitude exceed the limitation of DDS.


So my question is:

1. If keep using the 3.3V oscillator to supply REFCLK, we need to attenuate the 3.3V signal down to 1Vpp, then how should we do this attenuation?

2. In my opinon, there are several methods to supply REFCLK:

  • we can use oscillator to supply the REFCLK;
  • also we can use some clock distribution chip(AD9510) to output LVDS or LVPECL signal, it can meet the requirement of DDS
  • FPGA output clock signal to DDS;

   in real application, which method the customer will use? Or maybe there are other methods to supply REFCLK.