The user guide on AD website is for HSC-ADc-EVALC. So the
Updated schematics for HSC-ADC-EVALCZ FIFO501B is needed to understand how to set J9 for the HSC-ADC-eVALcz fifo501B to work
with AD9653 eva board. Any one can help?
Please refer to the following ADI EngineerZone posting which discusses the FIFO501B revision history. The FIFO501B is simply our internal ADI part drawing # for the public/production “HSC-ADC-EVALCZ”. The link below also provides the latest FIFO501B schematic.
The FPGA I/O voltage compatibility is selected via the singlejumper (J9) as follows:
Thank you for evaluating the AD9653. The HSC-ADC-EVALC works fine with the AD9653 evaluation board, with J9 in the 2.5V position.
Are you seeing problems with J9 in the 2.5V position?
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