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AD9254 jitter for LVDS inverted P/N

Question asked by Vali on Jun 7, 2015
Latest reply on Jun 22, 2015 by pkern

We have few LVDS clocks from AD9254 with the pair P/N inverted on the board (P will go to N and N to P on the receiver).

Should I be worry the jitter is any different that what is specified in the datasheet? We will be using rising edges in our application but due to this inversion we'll end up using falling edge of the clock generated by AD9254.

I understand we could have duty cycle variation,  but we use only one edge in our application.

Thanks for your help,